In recent years, a gate breakdown type anti-fuse has been used in relief circuits of a dynamic random-access memory (DRAM). Together with the large capacity structure and miniaturization of the DRAM devices, the number of defects caused by defective parts has increased. As a result, there has been an increase in the number of anti-fuses included in DRAM devices for relieving the defects. In order to reduce the area of these anti-fuse circuits within a chip, a system for arranging the anti-fuses in an array has been used. However, because it is difficult to carry out breakdown processes of anti-fuses in a stable manner and because of the large increase in a number of anti-fuses, chip yield can be impacted because even a single anti-fuse failure can make the chip defective.